This question lingered in the background of the closing panel at DAC yesterday, and it prompted several very interesting observations from the panelists. There was some agreement that IP-XACT, with ...

Time was when designing an ASIC meant generating RTL, from scratch, for every block in the design. As chip capacities grew larger, this approach became less efficient and, eventually, impractical. For ...

Some of the interesting action at DAC is always in the vendor-sponsored events in the surrounding hotels. One example this year was a panel, sponsored by memory IP vendor Sidense and recent Cadence ...

With so few SoC designs — if any — today designed completely new from the ground up, the assembly task is an extremely important one to get right. IP components must be put together optimally and ...

Semiconductor industry's most experienced network-on-chip interconnect IP and SoC IP integration software companies to simplify chip delivery for the AI/ML era CAMPBELL, Calif. – October 1, 2020 – ...

Semiconductor design is rapidly evolving because technologies such as AI and machine learning (ML) applications push the boundaries of complexity and specialization. Modern chips require hundreds or ...